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Parallel test execution - streamlining System on Chip verification flow

Freescale Semiconductor
Published:  Jul 07, 2011
Length:  3 pages

System on Chip is a large scale design that involves a complex set of verification environments, the number of verification stimulus can run into the thousands from several design sources. The effort in running these vectors is enormous. Merging test vectors is a process not trivial in such a large environment but is an effort worth considering when developing a SoC. This paper outlines the steps required in order to reach parallel execution of testing vectors and increase resource efficiency.



Tagssoc parallel verification, system on a chip